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 MCR8DCM, MCR8DCN
Preferred Device
Silicon Controlled Rectifiers
Reverse Blocking Thyristors
Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. * Small Size * Passivated Die for Reliability and Uniformity * Low Level Triggering and Holding Characteristics * Available in Surface Mount Lead Form -- Case 369A * Device Marking: Logo, Device Type, e.g., MCR8DCM, Date Code
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SCRs 8 AMPERES RMS 600 thru 800 VOLTS
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Peak Repetitive Off-State Voltage(1) (TJ = -40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR8DCM MCR8DCN Symbol VDRM, VRRM 600 800 8.0 5.1 80 Amps Amps Amps 12 3 Value Unit Volts A
G K
4
On-State RMS Current IT(RMS) (180 Conduction Angles; TC = 105C) Average On-State Current (180 Conduction Angles; TC = 105C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 msec) Forward Peak Gate Power (Pulse Width 1.0 msec, TC = 105C) Forward Average Gate Power (t = 8.3 msec, TC = 105C) Forward Peak Gate Current (Pulse Width 1.0 msec, TC = 105C) Operating Junction Temperature Range Storage Temperature Range IT(AV) ITSM
D-PAK CASE 369A STYLE 4
I2t PGM PG(AV) IGM TJ Tstg
26 5.0 0.5 2.0 - 40 to 125 - 40 to 150
A2sec 1 Watts Watts Amps C C 2 3 4
PIN ASSIGNMENT
Cathode Anode Gate Anode
ORDERING INFORMATION
Device MCR8DCMT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 16mm Tape and Reel (2.5K/Reel)
(1) VDRM, VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded.
MCR8DCNT4
DPAK 369A
Preferred devices are recommended choices for future use and best overall value.
(c) Semiconductor Components Industries, LLC, 1999
1
February, 2000 - Rev. 1
Publication Order Number: MCR8DCM/D
MCR8DCM, MCR8DCN
THERMAL CHARACTERISTICS
Characteristic Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Thermal Resistance -- Junction to Ambient(1) Maximum Lead Temperature for Soldering Purposes(2) Symbol RqJC RqJA RqJA TL Max 2.2 88 80 260 Unit C/W
C
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristics Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Repetitive Forward or Peak Repetitive Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM mA -- -- -- -- 0.01 5.0
ON CHARACTERISTICS
Peak On-State Voltage(3) (ITM = 16 A) Gate Trigger Current (Continuous dc) (VAK = 12 V, RL = 100 W, TJ = 25C) (TJ = -40C) Gate Trigger Voltage (Continuous dc) (VAK = 12 V, RL = 100 W, TJ = 25C) (TJ = -40C) (TJ = 125C) Holding Current (VAK = 12 V, Initiating Current = 200 mA, Gate Open) Latching Current (VAK = 12 V, IG = 15 mA, TJ = 25C) (VAK = 12 V, IG = 30 mA, TJ = -40C) TJ = 25C TJ = -40C IL 4.0 -- 22 -- 30 60 VTM -- IGT 2.0 -- VGT 0.5 -- 0.2 IH 4.0 -- 22 -- 30 60 mA 0.65 -- -- 1.0 2.0 -- mA 7.0 -- 15 30 Volts 1.4 1.8 mA Volts
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Off-State Voltage (VAK = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) (1) Surface mounted on minimum recommended pad size. (2) 1/8 from case for 10 seconds. (3) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. dv/dt 50 200 -- V/ms
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2
MCR8DCM, MCR8DCN
Voltage Current Characteristic of SCR
+ Current Anode + VTM on state IRRM at VRRM IH
Symbol
VDRM IDRM VRRM IRRM VTM IH
Parameter
Peak Repetitive Off State Forward Voltage Peak Forward Blocking Current Peak Repetitive Off State Reverse Voltage Peak Reverse Blocking Current Peak On State Voltage Holding Current Reverse Blocking Region (off state) Reverse Avalanche Region Anode -
+ Voltage IDRM at VDRM Forward Blocking Region (off state)
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C)
P(AV) , AVERAGE POWER DISSIPATION (WATTS)
125
10 180 8.0
120
a
a
120 90 dc 60
115
a = Conduction
Angle
6.0
a = Conduction
Angle
110 dc
4.0
a = 30
105
2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 IT(AV), AVERAGE ON-STATE CURRENT (AMPS)
a = 30
0 1.0 2.0
60 3.0
90 4.0
120 5.0
180 6.0
100 IT(AV), AVERAGE ON-STATE CURRENT (AMPS)
Figure 1. Average Current Derating
Figure 2. On-State Power Dissipation
I T, INSTANTANEOUS ON-STATE CURRENT (AMPS)
100 TYPICAL @ TJ = 25C MAXIMUM @ TJ = 125C 10 r(t) , TRANSIENT RESISTANCE (NORMALIZED)
1.0
0.1 ZqJC(t) = RqJC(t)Sr(t)
MAXIMUM @ TJ = 25C 1.0
0.1 0 1.0 2.0 3.0 4.0 5.0 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
0.01 0.1 1.0 10 100 1000 10 K t, TIME (ms)
Figure 3. On-State Characteristics
Figure 4. Transient Thermal Response
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3
MCR8DCM, MCR8DCN
100 VGT, GATE TRIGGER VOLTAGE (VOLTS) 35 I GT, GATE TRIGGER CURRENT (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 5.0 20 50 65 80 95 110 125 -40 -25 -10 5.0 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
10
1.0 -40 -25 -10
Figure 5. Typical Gate Trigger Current versus Junction Temperature
100 100
Figure 6. Typical Gate Trigger Voltage versus Junction Temperature
10
IL, LATCHING CURRENT (mA) 5.0 20 35 50 65 80 95 110 125
IH , HOLDING CURRENT (mA)
10
1.0 -40 -25 -10
1.0 -40 -25 -10
5.0
20
35
50
65
80
95
110
125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 7. Typical Holding Current versus Junction Temperature
Figure 8. Typical Latching Current versus Junction Temperature
1000 VD = 800 V TJ = 125C STATIC dv/dt (V/ ms) 100 10 100 1000 10 K RGK, GATE-CATHODE RESISTANCE (OHMS)
Figure 9. Exponential Static dv/dt versus Gate-Cathode Resistance
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4
MCR8DCM, MCR8DCN
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
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5
MCR8DCM, MCR8DCN
PACKAGE DIMENSIONS
D-PAK CASE 369A-13 ISSUE Z
-T- B V R
4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.175 0.215 0.020 0.050 0.020 --- 0.030 0.050 0.138 --- CATHODE ANODE GATE ANODE MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.45 5.46 0.51 1.27 0.51 --- 0.77 1.27 3.51 ---
C E
A S
1 2 3
Z U
K F L D G
2 PL
J H 0.13 (0.005) T
DIM A B C D E F G H J K L R S U V Z
M
STYLE 4: PIN 1. 2. 3. 4.
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6
MCR8DCM, MCR8DCN
Notes
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7
MCR8DCM, MCR8DCN
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
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8
MCR8DCM/D


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